1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and a method of manufacturing the same.
2. Discussion of the Related Art
Liquid crystal display (“LCD”) devices are driven based on electro-optical characteristics of a liquid crystal material. The liquid crystal material has an intermediate state between a solid crystal and an isotropic liquid. The liquid crystal material is fluid like an isotropic liquid, and molecules of the liquid crystal material are regularly arranged like a solid crystal. An alignment direction of the liquid crystal molecules depends on the intensity or the direction of an electric field applied to the liquid crystal molecules. Light passes through the LCD device along the alignment direction of the liquid crystal molecules. By controlling the intensity or the direction of the electric field, the alignment direction of the liquid crystal molecules changes, and images are displayed.
Active matrix liquid crystal display (“AMLCD”) devices, which include thin film transistors as switching devices for a plurality of pixels, have been widely used due to their high resolution and ability to display fast moving images.
Generally, an LCD device includes two substrates, which are spaced apart and facing each other, and a liquid crystal layer interposed between the two substrates. Each of the substrates includes an electrode. The electrodes of the respective substrates face one the other. An electric field is induced between the electrodes by applying a voltage to each electrode. An alignment direction of liquid crystal molecules changes in accordance with a variation in the intensity or the direction of the electric field. The direction of the electric field is perpendicular to the substrates. The LCD device has relatively high transmittance and a large aperture ratio.
However, the above-described LCD device has a narrow viewing angle. To increase the viewing angles, various modes have been proposed. Among these modes, an IPS mode of the related art will be described with reference to the accompanying drawings.
FIG. 1 is a schematic cross-sectional view of an IPS mode LCD device according to the related art.
In FIG. 1, the IPS mode LCD device according to the related art includes a lower substrate 10 and an upper substrate 40, and a liquid crystal layer LC is interposed between the lower substrate 10 and the upper substrate 40.
A thin film transistor T, a common electrode 18 and a pixel electrode 30 are formed at each pixel P on the lower substrate 10. The thin film transistor T includes a gate electrode 14, a semiconductor layer 22, and source and drain electrodes 24 and 26. The semiconductor layer 22 is disposed over the gate electrode 14 with a gate insulating layer 20 therebetween. The source and drain electrodes 24 and 26 are formed on the semiconductor layer 22 and are spaced apart from each other.
The common electrode 18 includes a plurality of portions, and the pixel electrode 30 includes a plurality of parts. The portions of the common electrode 18 and the parts of the pixel electrode 30 are parallel to and spaced apart from each other on the lower substrate 10. The common electrode 18 may be formed of the same material and in the same layer as the gate electrode 14. The pixel electrode 30 may be formed of the same material and in the same layer as the source and drain electrodes 24 and 26.
Although not shown in the figure, a gate line is formed along a first side of the pixel P, and a data line is formed along a second side of the pixel P perpendicular to the first side. A common line is further formed on the lower substrate 10. The common line provides the common electrode 18 with a voltage.
A black matrix 42 and a color filter layer 44 are formed on an inner surface of the upper substrate 40. The black matrix 42 is disposed over the gate line, the data line and the thin film transistor T. The color filter layer 44 is disposed at the pixel P.
Liquid crystal molecules of the liquid crystal layer LC are driven by a horizontal electric field 35 induced between the common electrode 18 and the pixel electrodes 30.
The lower substrate 10 including the thin film transistor T, the common electrode 18 and the pixel electrode 30 may be referred to as an array substrate. The upper substrate 40 including the black matrix 42 and the color filter layer 44 may be referred to as a color filter substrate.
As stated above, the common electrode 18 is formed of the same material and on the same layer as the gate electrode 14, and the pixel electrode 30 is formed of the same material and on the same layer as the source and drain electrodes 24 and 26. Since the common electrode 18 and the pixel electrode 30 are formed of an opaque conductive material, regions for the common electrode 18 and the pixel electrode 30 are not included in an aperture area. The aperture ratio decreases, and thus the brightness is lowered.
To solve the problem, the pixel electrode has been formed of a transparent conductive material.
FIG. 2 is a plan view of an array substrate for another IPS mode LCD device according to the related art.
In FIG. 2, gate lines 52 are formed along a first direction on a substrate 50. Data lines 70 are formed along a second direction. The data lines 70 cross the gate lines 52 to define pixel regions P. A common line 56 is formed between adjacent gate lines 52 along the first direction. The common line 56 is disposed along a side of the pixel region P.
A thin film transistor T is formed at each crossing point of the gate and data lines 52 and 70. The thin film transistor T includes a gate electrode 54, an active layer 62, a source electrode 66 and a drain electrode 68. The gate electrode 54 is connected to the gate line 52. The active layer 62 is formed over the gate electrode 54 with a gate insulating layer (not shown) therebetween. The source and drain electrodes 66 and 68 are spaced apart from each other over the active layer 62. The source electrode 66 is connected to the data line 68.
A common electrode 58 and a pixel electrode 76 are formed in each pixel region P. The common electrode 58 includes portions extending from the common line 56 along the second direction, and the common electrode 58 is formed of the same material and on the same layer as the gate line 52. The pixel electrode 76 contacts the drain electrode 68 and includes parts extending along the second direction. The portions of the common electrode 58 alternate with the parts of the pixel electrode 76. The common electrode 58 is formed of an opaque conductive material, and the pixel electrode 76 is formed of a transparent conductive material.
Even though the pixel electrode is transparent, light is not transmitted all over the pixel electrode. That is, some areas of the pixel electrode under the electric field induced between the pixel electrode and the common electrode can be used for the aperture ratio. However, the brightness of the IPS mode LCD device is fairly increased on the whole when the pixel electrode is formed of a transparent conductive material.
Accordingly, in an IPS mode LCD device including the array substrate of FIG. 2, since the pixel electrode 76 is transparent, the brightness is fairly improved as compared with the IPS mode LCD device of FIG. 1.
FIGS. 3A to 3E illustrate processes of manufacturing an array substrate according to the related art. FIGS. 3A to 3E are cross-sectional views corresponding to the line III-III of FIG. 2.
FIG. 3A shows an array substrate in a first mask process. In FIG. 3, switching regions S and pixel regions P are defined on a substrate 50. Each pixel region P includes one switching region S. Gate lines 52 of FIG. 2 and gate electrodes 54 are formed on the substrate 50. Each gate electrode 54 is disposed in the switching region S and is connected to each gate line 52 of FIG. 2. A common line 56 of FIG. 2 is also formed between adjacent gate lines 52 of FIG. 2 on the substrate 50, and a common electrode 58 is formed at each pixel region P on the substrate 50. Although not shown in the figure, the gate lines 52 of FIG. 2 and the common line 56 of FIG. 2 extend along a first direction. The common electrode 58 includes portions extending from the common line 56 of FIG. 2 along a second direction crossing the first direction.
A gate insulating layer 60 is formed substantially on an entire surface of the substrate 50 including the gate lines, the gate electrode 54, the common electrode 58, and the common line by depositing one selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2).
FIG. 3B shows an array substrate in a second mask process. In FIG. 3B, an active layer 62 and an ohmic contact layer 64 are formed on the gate insulating layer 60 over the gate electrode 54 by depositing intrinsic amorphous silicon (a-Si:H) and impurity-doped amorphous silicon (for example, n+a-Si:H) substantially on an entire surface of the substrate 50 including the gate insulating layer 60 and patterning them.
FIG. 3C shows an array substrate in a third mask process. In FIG. 3C, source and drain electrodes 66 and 68 are formed on the ohmic contact layer 64 by depositing a metallic material substantially on an entire surface of the substrate 50 including the active layer 62 and the ohmic contact layer 64 thereon and then patterning it. The source and drain electrodes 66 and 68 are spaced apart from each other. Data lines 70 are formed simultaneously with the source and drain electrodes 66 and 68. The data lines 70 are connected to respective source electrodes 66. Although not shown in the figures, the data lines 70 extend along the second direction and cross the gate lines 52 of FIG. 2 to define the pixel regions P. Each data line 70 is disposed between adjacent pixel regions P. The metallic material may be one or more selected from a conductive metallic group including aluminum (Al), an aluminum alloy such as aluminum neodymium (AlNd), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti) and molybdenum-tungsten (MoW).
Next, a part of the ohmic contact layer 64 is removed between the source and drain electrodes 66 and 68, thereby exposing the active layer 62.
FIG. 3D shows an array substrate in a fourth mask process. In FIG. 3D, a passivation layer 72 is formed substantially on an entire surface of the substrate 50 including the source and drain electrodes 66 and 68 by depositing one selected from an inorganic insulating material group including silicon nitride (SiNX) and silicon oxide (SiO2) or coating the substrate 50 with one or more selected from an organic insulating material group including benzocyclobutene (BCB) and acrylic resin. The passivation layer 72 is patterned to thereby form a drain contact hole exposing a part of each drain electrode 68.
FIG. 3E shows the array substrate in a fifth mask process. In FIG. 3E, a pixel electrode 76 is formed at each pixel region P on the passivation layer 72 by depositing a transparent conductive material substantially on an entire surface of the substrate 50 including the passivation layer 72 and then patterning it. The transparent conductive material is selected from a transparent conductive metallic group including indium tin oxide (ITO) and indium zinc oxide (IZO). The pixel electrode 76 is connected to the drain electrode 68 through the drain contact hole 64. The pixel electrode 76 includes parts spaced apart from and alternating with the portions of the common electrode 58.
The array substrate including the transparent pixel electrode 76 may be manufactured using the above-mentioned 5 mask processes. However, various trials still have been made to further improve the brightness of the LCD device. To do this, a transparent common electrode has been proposed.
FIG. 4 is a cross-sectional view of another array substrate for an IPS mode LCD device according to the related art. In FIG. 4, switching regions S and pixel regions P are defined on a substrate 50. Each pixel region P includes one switching region S. A thin film transistor T is formed in the switching region S. The thin film transistor T includes a gate electrode 54, a gate insulating layer 60, an active layer 62, an ohmic contact layer 64, a source electrode 66, and a drain electrode 68. A data line 70 is disposed between adjacent pixel regions P. The data line 70 is formed of the same material and on the same layer as the source and drain electrodes 66 and 68.
Although not shown in the figure, gate lines and a common line between adjacent gate lines are formed on the substrate 50 and cross the data line 70.
A passivation layer 72 covers the thin film transistor T and the data line 70. A pixel electrode 76 and a common electrode 78 are formed in each pixel region P on the passivation layer 72. The pixel electrode 76 contacts the drain electrode 68, and the common electrode 78 contacts the common line (not shown).
The pixel electrode 76 and the common electrode 78 are formed of a transparent conductive material. Liquid crystal molecules over edge areas E of each part of the pixel electrode 76 and each portion of the common electrode 78 are affected by an electric field induced between the pixel and common electrodes 76 and 78. The edge areas E are utilized as the aperture area.
Since the pixel electrode and the common electrode are transparent, an IPS mode LCD device including the array substrate of FIG. 4 has a more improved brightness than that of the array substrate of FIG. 2. The array substrate of FIG. 4 may be manufactured using 5 mask processes in the same way as the array substrate of FIG. 2.
However, central areas C of each part of the pixel electrode 76 and each portion of the common electrode 78 cannot be utilized as the aperture area. There may be a leakage of light in the central areas C. When the device shows black, the leakage of light may cause a disclination line. This decreases the contrast ratio of the device.